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[ AK8142 ] ms0932 - j - 01 2009/1 - 1 - ak 8142 programable clock generator ic AK8142 ?? i ???? ? ??` ic ? ? ? ? ??k ? ? ?? ? O ???? L ??R 3.0 v - 3.6v ???` ?R 1.8v 3.3 v M 5.5ma typ. ? k? 16.0mhz 32.0mhz ? 2.0mhz 67.0mhz ? : 4mhz 200mhz ? ?????` ??` 16 ? tssop ( U ?` ) ? : N ??`??? crystal osc vdd x out x in extin ck out reset fs e l sda scl a0 a1 gnd 1 control register0 refout phase comparator charge pump lpf n div S modulator odiv mdiv frac[17:0] int [ 6 :0] ckouten [1:0] out c[ 2 :0] odivpg [ 3 :0] mdivpg [ 2 :0] mdivc [ 3 :0] ckoff [0] ckoff [ 1 ] refouten [1:0] ?? ( ? ) ? ? ? ???
[ AK8142 ] ms0932 - j - 01 2009/1 - 2 - 1. h ? C h ? cdg ( ) h 1 xin xi ???A / ? ? . 2 reset di ?? . ? pll ? reset ? . h: reset l: ? 3 fs el di ?O ? xk ? e ? ? ? 4 vdd1 pwr ? 3.3v ? 5 gnd1 pwr 6 2 pwr 2. 7 vdd2 pwr ? 2 1.8 3.3v ? ? ??? 8 ckout do ? 9 refout do pll ? 10 scl di ? ?` ? 11 sda dio ? ?` ` 12 vdd3 pwr ? 3 1.8v 3.3v( ???? ? ??????? ) 13 gnd3 pwr 3 ???? ? ??????? 14 a1 di i c ? O 1. 15 a0 di i c ? O 0. 16 xout xo ???A ? ? r _ ? ? . pwr ? do ? di ? d io ? xi: ???A ,xo: ???A 1 :x in 2: re set 3:fsel 4:vdd1 5:gnd1 6:gnd2 7:vdd2 8:c k out 16 :x out 15:a0 14:a1 13:gnd 12:vdd3 11:sda 10:scl 9:refout
[ AK8142 ] ms0932 - j - 01 2009/1 - 3 - 2. ?? 2 1 ~?? ? ? ? ? ?? ? ? ? ^ 2 2 2 3 M vdd1=3.3v, vdd2=vdd3=1.8v, ta=25 x in = 16.0 mhz ,ckout 24.5759989mhz, ? ? ` scl=h sda=h o??r ? O ff=03hex fe=74hex,fd=bchex fc=25hex fb=32hex fa=61h ex ? ? min max g vw ? R vdd - 0.3 4.6 v ? vss 0 0 v R vin vss - 0.3 vdd+0.3 v iin - 10 10 ma ? tstg - 55 130 ? ? min typ max g vw ? ta - 3 0 85 vdd1 3.0 3.3 3.6 v ? R vdd2 vdd3 1.7 1.8 vdd1 v cplclk 15 10 8 pf clkout 100mh 150mh 200mh ? cplref 25 refout 6 7 mhz ? ? min typ max g v w M idd1 4.4 ma M idd2 0.95 ma M idd 0.05 ma
[ AK8142 ] ms0932 - j - 01 2009/1 - 4 - 2 4 vdd 3.3v vdd2=vdd3=1.8v,ta - 3 0 85 * 1 sda,scl R vdd3(2 ?? ?` ? ) ? ? ? ? ? min typ max g q ?? ? ? R 1 0.7*vdd1 v ?? ? ? R 1 a0/a1 fsel reset 0.3*vdd 1 v ?? ? ? R 2 0.7*vdd 3 v * 1 ?? ? ? R 2 scl/sda 0.3*vdd 3 v ?? ? ? R 1 0.8*vdd 2 v ioh= - 4ma ?? ? ? R 1 refout clkout 0.2*vdd 2 v iol=4m a ?? ? ? R 2 sda 0.4 v iol=3ma o pen drain ??? a0/a1 fsel reset - 10 +10 ua
[ AK8142 ] ms0932 - j - 01 2009/1 - 5 - 2 5 a vdd 3.3v vdd2 - vdd3=1.8v ta - 3 0 85 *1 O ? *2 ^ ? = ? /mdiv fa ? *3 vco k ? ^ ? ndiv fc ? *4 fb ? *5 ? ? *6 ? ??r ? clk ` ? ` *7 fsel ? ? 0.1% _ ?? r g ? min typ max g q k ? xin xout 16.0 24.0 32.0 mhz * 1 ? ??r ? ? xin 2.0 6 7. 0 mhz ? ` r 0.8 vpp ? ? ? ? ? ?? ? ? ??? xin 30 50 70 % *1 ? ` r ^ 2 4 mh *2 ? vco k ? ckout 100 mh *3 4.0 100 mhz *4 ? ? ckout 100 200 mhz *4 o refout 3.0 n s *1,*5 0.2vdd - >0.8vdd 2mhz 66mh 3.0 n s *1,*5 0.2vdd - >0.8vdd 4mhz 100mh 2.5 n s *1,*5 0.2vdd - >0.8vdd 150mhz clk r g ckout 2.0 n *1,*5 0.2vdd - >0.8vdd 200mhz refout 3.0 n s *1,*5 0.8vdd - >0.2vdd 2mhz 66mh 3.0 n s *1,*5 0.8v dd - >0.2vdd 100mh 2.5 n s *1,*5 0.8vdd - >0.2vdd 150mhz clk r g ckout 2.0 n *1,*5 0.8vdd - >0.2vdd 200mhz ? ? ? ?? ? ? ? ?? (1 ) ckout 20 p s *1,*5 refout 40 50 60 *1,*5 *6 45 50 55 *1,*5 ? ? ? ? ? ?? ? ? ??? ckout 30 50 70 % *1,*5 o ? ?? r g ckout 1 m s *7
[ AK8142 ] ms0932 - j - 01 2009/1 - 6 - 2 - 6 ? ac 2 ? ? i/f `?` vdd 3.3v vdd2 - vdd3=1.8v ta - 30 85 ? ? min. max . g q scl ? scl 400 khz scl low g low 1.3 s scl high g high 0.6 s R ? i 50 ns scl low sda out _ aa 0.1 3.5 s _?r g buf 1.3 s ` ?? ?? su.sta 0.6 s ???? ?? su.sto 0.6 s sda in ` hd.dat 0 s sda in ? ?? su.dat 0.1 s w r g r 0.3 s * 1 w r g f 0.3 s * 1 sda out ` dh 0.1 s * 1 O ? scl (in) sda (in) sda ( out) tf tr tsu.sta tsu.sto tsu.dat thd.dat taa tdh tbuf tlow thigh
[ AK8142 ] ms0932 - j - 01 2009/1 - 7 - 3. Ch 3 - 1 2 ? ????` 2 ? ?? ?` i/f ` / ? ? AK8142 ? ? ? ? ? ? a0,a1 O ?? 3 - 1 AK8142 ? 3.1.1 ? 3 - 2 ? ? ? ? ? z ` ? 3 - 2 ? 1 0 1 0 device address device address 0 r w address (msb first) data (msb first) s t a r t sda -1 -2 / a c k a c k a c k s t o p 3.1.2 ?` ? 3 - 3 ` ? ? ? ` ? 8 ? ? 4 ? ? ? 4 ? ? 1111 1111 z z ? 1111 0000 ??? 3 - 3 ` ? device address device address r w address (msb first) data ( address ) s t a r t sda -1 -2 / a c k a c k a c k data a c k ( address +1 ) 1 0 1 0 0 a c k s t o p data a c k ( address +n ) ???? 3.1.3 ? ?? ? ` 3 - 4 ? ? ? ` ? ? i ` ? +1 ?? ? 1111 1111 i ? 1111 0000 ??? 3 - 4 ? ? ? ` 1 0 1 0 device address device address 1 r w data (msb first) s t a r t sda -1 -2 / a c k n o a s t o p c k 1 0 1 0 1 a1 a0 r/w device adress#2 device adress#1
[ AK8142 ] ms0932 - j - 01 2009/1 - 8 - 3.1.4 ? ` 3 - 5 ? ` ? ? ? ` ` i ? ` k ? 3 - 5 ? ` 1 0 1 0 device address device address 0 r w address (msb first) s t a r t sda -1 -2 / a c k a c k s t a r t 1 0 1 0 device address -1 n o a s t o p c k dummy write device address 1 r w -2 / a c k data (msb first) 3.1.5 BA ` 3 - 6 B A ` ? ? ` ? ? ` ` ?? o ack ? ` i ? ? ? 1111 1111 i ? 1111 0000 ??? 3 - 6 B A ` sda device address 1 r w -2 / a c k data (msb first) ( address ) n o a s t o p c k a c k data (msb first) (address+1 ) a c k ???? a c k data (msb first) (address+ n ) ???? 3.1.6 ?` 3 - 7 ` ? ? ` sda scl l r ?? 3 - 7 ` sda scl data stable data change 3.1.7 ` / ?? 3 - 8 ` / ?? ? ? scl h r sda h l ? ` ?? sda l h ? ?? ??? 3 - 8 ` / ?? sda scl start stop
[ AK8142 ] ms0932 - j - 01 2009/1 - 9 - 3 2 ??? fa ff Q f7 ? bank,bankwr,ctlfsel ? i ? ? ?? ? sftrst ?? ?`?? ?? ? ? ? ? ?? d7 d6 d5 d4 d3 d2 d1 d0 q frac[17] frac[16] ff 0 0 frac[15] frac[14] frac[13] frac[12] frac[11] frac[10] frac[9] frac[8] fe 0 0 0 0 0 0 0 0 frac[7] fra c[6] frac[5] frac[4] frac[3] frac[2] frac[1] frac[0] fd 0 0 0 0 0 0 0 0 S int[6] int[5] int[4] int[3] int[2] int[1] int[0] fc 0 0 0 0 0 0 S outc[2] outc[1] outc[0] odivpg[3] odivpg[2] odivpg[1] odivpg[0] fb 0 outdiv mdivc[3] mdivc[2] mdivc[1] mdivc[0] mdivp[3] mdivp[2] mdivp[1] mdivp[0] fa 0 0 0 0 0 mdiv f9 0 0 s f8 0 0 0 0 s bank bankwr ctlfsel ckoff[1] ckoff[0] ?l ?? f7 0 0 0 1 0 0 0 0 ? ? ? ? bank ckouten [1] refoten [0] refoten [1] refoten [0] f6 0 0 0 0 outbuf dumon dither f5 0 1 S f4 f1 f1 f4 ? ? ?
[ AK8142 ] ms0932 - j - 01 2009/1 - 10 - 3 3 ? Ch ?O ? ] ? n O ? ? ? ?? d7 d6 d5 d4 d3 d2 d1 d0 frac[17] frac[16] frac[15] frac[14] frac[13] frac[12] frac[11] frac[ 10] frac[9] frac[8] frac[7] frac[6] frac[5] frac[4] frac[3] frac[2] frac[1] frac[0] frac[17:0] fractional n O frac[17:0] a 01 1111 1111 1111 1111 +131071 0.49999619.. 01 1111 1111 1111 1110 +131070 01 0000 0000 0000 0000 +65536 0.25 00 0000 0000 0000 0001 +1 0.00000381.. 00 0000 0000 0000 0000 0 0 11 1111 1111 1111 1111 - 1 - 0.00000381.. 11 1111 1111 1111 1110 - 2 11 0000 0000 0000 0000 - 65536 - 0.25 10 0000 0000 0000 0001 - 131071 - 0.49999619.. 10 0000 0000 0000 0000 - 131072 - 0.5 a/2 18 ? ? frac O ? frac[17:0] a F - 2 17 +2 17 ? O ?? - 0.5 +0.5 ? O ?? ?? ff frac[ 17 : 0 ] ? fd,fe,ff z ? ?? ? ? n O ? ? ? ?? d7 d6 d5 d4 d3 d2 d1 d0 int[6] int[5] int[4] int [3] int[2] int[1] int[0] int[5:0] fractional n O int[6:0] 000 0000 001 1000 O ? ? 001 1001 25 001 1010 26 110 0011 99 110 0100 100 110 0101 111 1111 O ? * ? O 25 100 ? ?
[ AK8142 ] ms0932 - j - 01 2009/1 - 11 - ? O ? ? ? ?? d7 d6 d5 d4 d3 d2 d1 d0 b outc[2] outc[1] outc[0] odivpg[3] odivpg[2] odivpg[1] odivpg[0] outc[2] ? xk 0 vco 1 vco outc[1:0] pll xk outc[1:0] 0 0 vco ? 0 1 vco 1 0 vco 1 1 vco ? odivpg[3:0] ? odivpg[3:0 ] x 0 0 0 0 ( ) 0 0 0 1 4 0 0 1 0 6 0 0 1 1 8 0 1 0 0 10 0 1 0 1 12 0 1 1 0 14 0 1 1 1 16 1 0 0 0 18 1 0 0 1 20 1 0 1 0 22 1 0 1 1 24 1 1 0 0 26 1 1 0 1 28 1 1 1 0 30 1 1 1 1 ( ) 1/4 1/2 1/2 programmable div. s e l pllout odiv outc[1:0] odivp g [3:0] outc[2] vco s e l
[ AK8142 ] ms0932 - j - 01 2009/1 - 12 - ? a refclk O ? ? ? ?? d7 d6 d5 d4 d3 d2 d1 d0 a mdivc[3] mdivc[2] mdivc[1] mdivc[0] mdivp[3] mdivp[2] mdivp[1] mdivp[0] mdivc[3] ? xk 0 clkin 1 clkin 2 mdivc[2] 3or4 xk 0 3 1 4 mdivc[1:0] m mdivc[1:0] 0 0 1 0 1 2 1 0 3or4 1 1 ? mdivp[3:0] ? mdivp[3:0] 0 0 0 0 O ? 0 0 0 1 2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1 16 1/3 or 1/4 1/2 1/2 programmable div. s e l m div m divc [1:0] m divp[3:0] mdiv c[ 3 ] s e l phase comparator clock in mdivc [ 2 ]
[ AK8142 ] ms0932 - j - 01 2009/1 - 13 - ? s ? ? ? ?? d7 d6 d5 d4 d3 d2 d1 d0 9 8 ? s ? 9 05hex 8 00hex O ? ? ?? O ? ? ? ?? d7 d6 d5 d4 d3 d2 d1 d0 bank bankwr ctlfsel ckoff[1] ckoff[0] eserved pd sftrst bank ?O xk 0 bank0 xk ctlfsel= 0 ? ? ? 1 bank1 xk ctlfsel= 0 ? ? ? bankwr bank z xk 0 bank0 z xk 1 bank1 z xk ctlfsel fsel C xk 0 m ?xk bank ? xk ? ? O ctlfsel C o ? ? 1 ? ?xk fsel ?B xk ? ckoff[1] ckout ` 0 1 off (500k pull_down) ckoff[0] refout ` 0 1 off (500k pull_down) reserved s ? ? 0 O ? pd pl l ` 0 ? 1 pll ? ` ??? sftrst ?? 0 ?? ? 1 ? ? ?? pll ? ? ?? ? O ?
[ AK8142 ] ms0932 - j - 01 2009/1 - 14 - ? ? ? ? ?? d7 d6 d5 d4 d3 d2 d1 d0 6 D D D D ckouten[1] ckouten[0] refouten[1] refouten[0] ckouten[1:0] ckout l ckouten[1:0] 0 0 0 1 1 0 1 1 refouten[1:0] refout l refouten[1:0] 0 0 0 1 1 0 1 1 ? O ? ? ? ?? d7 d6 d5 d4 d3 d2 d1 d0 5 D D D D D D dum on dither dumon S ` dumon 0 ? 1 S ` ? pll ? O ? dither ? n O dither 0 ? ? pll ? O ? 1 ? ? - ic ? ? ?
[ AK8142 ] ms0932 - j - 01 2009/1 - 15 - 3 4 O ckout ? ref clk mdiv odiv , ? ? ?? ?? ? n int,frac Q ? ` ? ? O ? vco ? Q ? fb ? vco ? fvco Q ? ? vco ? 100 z 200mhz ?? ? O ? ? 100mhz odiv ? ? ^? Q ^ ? 2mhz 4 z ?? ? O ? ?? Q vco ? (fvco) ^ ? cmp ? Q ? O 7 ? 18 ? a ??? int round fvco / ? round ( fvco / ) C 18 O 123.75 (1) ? 123.75 (2) ^ ? 3mhz mdiv = 9 27mhz/9 mh (3) ? 41.25 int 41 frac 65536 int = round (123.75/3) = round(41.25) = 41d frac = round (41.25 - 41) x 2 18 ) = 65536d ? ` ppm ? int[6:0]=29hex,frac[17:0]=10000hex O ? O ? O 0 f7 0 0 8 sftrst ?? bank0 ,fsel= o refout=off 0xfa 0x38 mdiv 9 0xfb 0x00 odiv 1 0xfc 0x29 int 41 0xfd 0x00 frac ? 0xfe 0x00 frac ? 0xff 0x01 frac ? frac=655536d
[ AK8142 ] ms0932 - j - 01 2009/1 - 16 - O 24.576 (1) ? 147.456 6 (2) ^ ? 4mhz mdiv = 4 16mhz/4 4mh (3) ? 36.864 int 37 frac - 35652 int = round (147.456/4) = round(36.864) = 37d frac = round (36.864 - 37) x 2 18 ) = - 35652d ? ` 0.043ppm 1.0 6 hz ? int[6:0]=25hex,frac[17:0]=374bchex O ? O ? O 0 f7 0 0 8 sftrst ?? bank0 fsel= o ,refout=off 0xfa 0x 0 6 mdiv 4 0xfb 0x 32 odiv 6 0xfc 0x 25 int 37 0xfd 0x bc frac 8 ? 0xfe 0x 74 frac 8 ? 0xff 0x0 3 frac 2 ? frac= - 35652 d
[ AK8142 ] ms0932 - j - 01 2009/1 - 17 - 3 5 ? ` vdd1/2/3 ? r ? reset ? ? ` ?? ? ? scl/sda ??? reset ?? reset usec scl/sda ??? vdd1 /2/3 ? ? ?? on ???? ? vref reset 2 ? ? ? ? ? ?? if min:500us scl/sda vdd*0.9 max :1ms ?? ?? ? ` ?? ? ? sftrst ? ??? ? ` ?? ^ ` ?? z ?? ?B ? reset ? r vref sftrst pwron rst ? sftrst ? ? ?? sft rst ? ? ??
[ AK8142 ] ms0932 - j - 01 2009/1 - 18 - 4. ` ? g 0.07 0.04 0 - 10 detail a seating plane | 0.10 0.17 0.05 0.22 0.08 0.65 5.00typ 1.10 max a 1 8 9 16 16pin ts sop (unit: mm) 4 . 4 t y p 6 . 4 0 . 2 0 . 5 0 . 2 1 . 1 0 m a x | 0.13|m 5. ` ? ? ` ? ??` ? ` xxxxx 5 8 9 16 xxxxx 8142
[ AK8142 ] ms0932 - j - 01 2009/1 - 19 - ? ? ?d u? u? ? ? u? ? ?? ? ? ? ? H ? d ?? ?I ?s?I _J d ? ? S I ? ? ? ? ? ? ?du? Q?? Y ( ? ) ? ? H ? ? S ? ? ? C ?? C ? C ? ? C ? ? g ?b p ? ? O m ? ? u? ? ? ? ? ? ? ? ? u? ? ? p ? ? ? ? ? ? ? ? ? ? u? ? ? p ? ? ? ? ? a ? ?

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